february 2006 copyright ? alliance semiconduc tor. all rights reserved. as7c4096a 5.0v 512k 8 cmos sram ? 2/21/06, v 1.2 alliance semiconductor p. 1 of 10 features ? pin compatible to as7c4096 ? industrial and commercial temperature ? organization: 524,288 words 8 bits ? center power and ground pins ? high speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time ? low power consumption: active - 880mw/max @ 10 ns ? low power consumption: standby - 55mw/max cmos ? equal access and cycle times ? easy memory expansion with ce , oe inputs ? ttl-compatible, three-state i/o ? jedec standard packages - 400 mil 36-pin soj - 44-pin tsop 2 ? esd protection 2000 volts ? latch-up current 200 ma logic block diagram 524,288 8 array (4,194,304) sense amp input buffer i/o8 i/o1 oe ce we column decoder row decoder control circuit a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 a10 a11 a12 a13 a14 a15 a16 a17 a18 a9 pin arrangement s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a15 oe i/o8 i/o7 gnd v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 17 18 a8 a9 36 35 34 33 nc a18 a17 a16 gnd v cc i/o6 i/o5 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 a8 a9 i/o8 i/o7 a1 a2 a3 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 a17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 nc nc nc nc nc nc nc nc nc oe a18 36-pin soj (400 mil) 44-pin tsop 2 selection guide ?10 ?12 ?15 ?20 unit maximum address access time 10 12 15 20 ns maximum outputenable access time 5 6 6 6 ns maximum operating current 160 140 120 100 ma maximum cmos standby current 10 10 10 10 ma
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 2 of 10 functional description the as7c4096a is a high-performance cmos 4,194,304-bit static random access memory (sram) device organized as 524,288 words 8 bits. it is de signed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with out put enable access times (t oe ) of 5/6 ns are ideal for high-performance applicatio ns. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the device is gu aranteed not to exceed 55mw power consumption in cmos standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1?i/o8 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input addres s. when either chip enable or output enable is inactive, or wr ite enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatib le, and operation is from a single 5.0v s upply voltage. this device is available as per industry standard 400-mil 36-pin soj and 44-pin tsop 2 packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational s ections of this spe cification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect reliability. absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.5 +7.0 v voltage on any pin relative to gnd v t2 ?0.5 v cc +0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c temperature with v cc applied t bias ?55 +125 c dc current into output (low) i out ?20ma truth table ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 3 of 10 * v ih max = v cc + 1.5v for pulse width less than 5 ns. ** v il min = ?1.0v for pulse width less than 5 ns. . recommended operating condition parameter symbol min nominal max unit supply voltage v cc (10/12/15/20) 4.5 5.0 5.5 v input voltage v ih * 2.2 ? v cc + 0.5 v v il ** ?0.5 ? 0.8 v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c dc operating characteristics (over the operating range ) 1 parameter symbol test conditions ?10 ?12 ?15 ?20 unit notes min max min max min max min max input leakage current |i li | v cc = max, v in = gnd to v cc ?1?1?1?1 a output leakage current |i lo | v cc = max, ce = v ih v out = gnd to v cc ?1?1?1?1 a operating power supply current i cc v cc = max, ce < v il f = f max , i out = 0ma ?160?140?120?100ma standby power supply current i sb v cc = max, ce > v ih f = f max , i out = 0ma ?60?55?50?40ma i sb1 v cc = max, ce v cc ? 0.2v, v in 0.2v or v in v cc ? 0.2v, f = 0 ?10?10?10?10ma output voltage v ol i ol = 6 ma, v cc = min ?0.4?0.4?0.4?0.4 v4 i ol = 8 ma, v cc = min ?0.5?0.5?0.5?0.5 v oh i oh = ?4 ma, v cc = min 2.4?2.4?2.4?2.4? v 4 c apacitance (f = 1mhz, t a = 25 c, v cc = nominal) 4 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 4 of 10 key to switching waveforms read waveform 1 (address controlled) 2,5,6,8 read waveform 2 (ce , oe controlled) 2,5,7,8 read cycle (over the operating range) 2,8 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max read cycle time t rc 10?12?15?20?ns address access time t aa ?10?12?15?20ns2 chip enable (ce ) access time t ace ?10?12?15?20ns2 output enable (oe ) access time t oe ?5?6?6?6ns output hold from address change t oh 3?3?3?3?ns4 ce low to output in low z t clz 3?3?3?3?ns3,4 ce high to output in high z t chz ?5?6?7?9ns3,4 oe low to output in low z t olz 0?0?0?0?ns3,4 oe high to output in high z t ohz ?5?6?7?9ns3,4 power up time t pu 0?0?0?0?ns3,4 power down time t pd ?10?12?15?20ns3,4 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 ce
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 5 of 10 write waveform 1 (we controlled) 9 write cycle (over the operating range) 9 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max write cycle time t wc 10?12?15?20?ns chip enable (ce ) to write end t cw 7?8?10?12?ns address setup to write end t aw 7?8?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7?8?10?12?ns write pulse width (oe = low t wp2 10?12?15?20?ns address hold from end of write t ah 0?0?0?0?ns write recovery time t wr 0?0?0?0?ns data valid to write end t dw 5?6?7?9?ns data hold time t dh 0?0?0?0?ns3,4 write enable to output in high z t wz 25262729ns3,4 output active fr om write end t ow 3?3?3?3?ns3,4 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 6 of 10 write waveform 2 (ce controlled) 9 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 for test conditions, see ac test conditions . 3t clz and t chz are specified with c l = 5pf as in figure b. transition is m easured 500 mv from steady-state voltage. 4 this parameter is guaranteed, but not tested. 5we is high for read cycle. 6ce and oe are low for read cycle. 7 address valid prior to or coincident with ce transition low. 8 all read cycle timings are referenc ed from the last valid address to the first transitioning address. 9 all write cycle timings are referen ced from the last valid address to the first transitioning address. 10 c = 30pf, except at high z and low z parameters, where c = 5pf. t aw address ce we t cw t dw t dh t ah t wc t as data valid d in t wr t wp 255 ? c 10 480 ? d out gnd +5.0v figure b: 5.0v output load - output load: see figure b. - input pulse level: gnd to v cc - 0.5v. see figures a and b. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 168 ? thevenin equivalent: d out +1.728v 10% 90% 10% 90% gnd v cc - 0.5v figure a: input pulse 2 ns
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 7 of 10 package dimensions 44-pin tsop 2 min(mm) max(mm) a 1.2 a 1 0.05 0.15 a 2 0.95 1.05 b 0.30 0.45 c 0.12 0.21 d 18.31 18.52 e 1 10.06 10.26 e 11.68 11.94 e 0.80 (typical) l 0.40 0.60 36-pin soj 400 min(mils) max(mils) a 0.128 0.148 a 1 0.025 ? a 2 0.105 0.115 b 0.015 0.020 b 1 0.026 0.032 c 0.007 0.013 d .920 .930 e 0.045 0.055 e 0.370 bsc e 1 0.395 0.405 e 2 0.435 0.445 d e 12 3 4 5 6 7 8 9 10 111213 14 44434241403938 37 36 35 34333231 15 16 30 29 17 1819 20 28 2726 25 c l a 1 a 2 e 44-pin tsop 2 0?5 21 24 23 e 1 a b seating plane 22 d pin 1 e e 1 e 2 a2 c a1 b b 1 a e 36-pin soj
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 8 of 10 note: add suffix ?n? to the above part number for lead free parts. (ex: as7c4096a - 10 tin) ordering codes package version 10 ns 12 ns 15 ns 20 ns soj commercial as7c4096a-10jc as7c4096a- 12jc as7c4096a-15jc as7c4096a-20jc industrial as7c4096a-10ji as7c4096a-12ji as7c4096a-15ji as7c4096a-20ji tsop 2 commercial as7c4096a-10tc as7c4096a-12tc as7c4096a-15tc as7c4096a-20tc industrial as7c4096a-10ti as7c4096a-12ti as7c4096a-15ti as7c4096a-20ti part numbering system as7c 4096a ?xx j or t x x sram prefix device number access time packages: j: soj 400 mil t: tsop 2 temperature ranges: c: commercial , 0c to 70c i: industrial, ?40c to 85c n=lead free parts
? as7c4096a 2/21/06, v 1.2 alliance semiconductor p. 9 of 10 revision history rev. no. history revised date v1.0 initial release 11/08/04 v1.1 included i cc , i sb & i sb1 parameters 05/27/05 corrected the following: t oe , v ih, v ol & t wz v1.2 removed the title ?preliminary information? 02/21/06
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c4096a document version: v 1.2 ? copyright 2003 alliance semiconductor corp oration. all rights reserved. our three-po int logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of th eir respective companies. alliance reserve s the right to make changes to this document and its products at any time without notice. alliance assumes no respon sibility for any errors that ma y appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product desc ribed herein is under development, signifi cant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customer s and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or cust omer. alliance does not assume any responsib ility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringe ment of any intellectual property rights, except as express ag reed to in alliance's terms and conditions of sale (which are available from alliance). all sa les of alliance products are made exclusively according to allian ce's terms and conditions of sale. the purchase of products from allianc e does not convey a license under any pate nt rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. allianc e does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to resu lt in significant injury to the user, and the inclusion of all iance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all clai ms arising from such use. as7c4096a ? ?
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